There has increasingly been a demand for faster, higher capacity random access memory (RAM) devices. At one time, dynamic random access memory (DRAM) was typically used as the main memory in computer systems. Although the operating speed of DRAM improved over the years, this speed did not reach the operating speed of the processors used to access the DRAM. In a computer system, for example, the slow access and cycle times of the DRAM led to system bottlenecks. These bottlenecks slowed down the throughput of the system despite the very fast operating speed of the computer system's processor.
As a result, a new type of memory known as synchronous dynamic random access memory (SDRAM) was developed to provide faster operation in a synchronous manner. SDRAMs are designed to operate synchronously with the computer system's clock. That is, the input and output data of the SDRAM are synchronized to an active edge of the computer system's clock.
Although SDRAMs have overcome some of the timing disadvantages of other memory devices, such as DRAMs, there is still a need for faster memory devices. Double data rate (DDR) SDRAMs provide twice the operating speed of conventional SDRAMs. These devices allow data transfers on both the rising and falling edges of the computer system's clock and thus provide twice as much data as the conventional SDRAM. DDR SDRAMs are also capable of providing burst data at a high-speed data rate.
Due to the high-speed data transfers, DDR SDRAMs use a bi-directional data strobe (DQS) to register the data being input or output on both edges of the computer system's clock. Industry standards define several states of DQS before, during, and after a burst transfer of data. Before a burst transfer of data, DQS is in a high-impedance state that is known as Hi-Z. When DQS is in Hi-Z, DQS is at a voltage level between logic high and logic low.
One clock cycle before a burst data transfer, DQS transitions from Hi-Z to logic low. This logic low state is known as “data strobe preamble.” After the data strobe preamble, DQS transitions (both low-to-high transitions and high-to-low transitions) are utilized to synchronize the transferred data. One half clock before the data transfer is completed, DQS remains in a logic low state. This state is known as “postamble.” After the completion of the postamble, DQS enters the Hi-Z state.
Thus, a need exists for a simple DQS receiver that can accurately determine DQS transitions and can avoid false determinations due to electrical noise.